1. Field of the Invention
The present invention relates to the field of direct memory transfers, specifically transfers across memory bus and a slower, external peripheral bus.
2. Art Background
As electronic technology improves, more and more elements are put on a single component. For example, on a processor component, it is desirable to include memory as well as other processor-supporting elements on the same component in order to take advantage of the high speed component-level interconnect available, as well as to minimize the amount of space required to implement the functionality. Thus, many of today's processor components, such as central processing units (CPU), can operate at extremely high speeds. However, the overall bandwidth of the system which includes the CPU is often limited by the speed of the external interconnect. Although specially designed memory busses typically operate on the processor clock, general purpose I/O busses cannot operate as fast. The external interconnect, for example, an I/O bus, can be three to five times slower than the intra-component buses. For example, one I/O bus, IEEE P1496 specification, is defined to support frequencies from 16.7 MHz to 25 MHz. Processor designs today start at 50 MHz and extend well above 100 MHz.